1. Field of Invention
The present invention relates to a structure for an electrostatic discharge (ESD) protection device. More particularly, the invention relates to a transistor structure having a different gate width.
2. Description of Related Art
In production of an integrated circuit, such as dynamic random access memory (DRAM) and static random access memory (SRAM), or after the manufacture of a wafer, damage caused by current leakage in the integrated circuit is often a result of an ESD occurring outside the integrated circuit. In the most common complementary metal oxide semiconductor (CMOS)technology, the ESD occurring outside the wafer causes severe damage to the wafer. Therefore, an ESD protection circuit is usually fabricated in the integrated circuit to direct the current to a ground before the current from the ESD enters an internal circuit. This prevents the damage caused by current entering the internal circuit.
To prevent the damaging effect of the ESD to the wafer, many types of software and hardware to restrain ESD have been developed. Conventionally, the most common method is to restrain the ESD with hardware, i.e. to design an ESD protection circuit between the internal circuit and each bonding pad to protect its internal circuit. As shown in FIG. 1, the design of the ESD protection circuit mainly connects an NMOS transistor between the bonding pad and the internal circuit and connects the NMOS transistor to the ground. Alternatively, a PMOS transistor is connected and this PMOS transistor is connected to a power line. As a result, when the current from the ESD is input via the bonding pad, the NMOS transistor and the PMOS transistor are turned on, and the current from the ESD is directed to the ground instead of the internal circuit.
FIG. 2 is a diagram showing the perspective view of a conventional transistor structure for an ESD protection device is provided. A gate structure 200 includes projecting parts 202 and a connecting part 204. The projecting parts 202 are parallel and isolated from each other by a distance, while the connecting part 204 which is located at one side of the gate structure 200, connects to the projecting parts 202. There are sources 208 and 208a as well as drains 206 alternating between projecting parts 202. The sources include a first source 208 located in the middle of the gate structure 200 and a second source 208a located further from the middle of the gate structure 200. There are contacts 212 in a row on each first source 208 and each drain 206, which connect the first source 208 and the drain 206 to the external circuit (not shown), respectively. In addition, a substrate junction 214 is connected to the second source 208a with a butting face and butting contacts 218 are formed in a row on the butting face.
FIG. 3 is across-sectional diagram illustrating the transistor structure along a 3--3 intersecting line in FIG. 2. It is understood from FIG. 3 that the projecting parts 202 are formed with a gate oxide layer 203 located below for electrical isolation and the butting contact 218 simultaneously connects to the second source 208a and the substrate junction 214. The butting contact 218 is used to reduce the resistivity between the second source 208a and the substrate junction 214. This prevents a latch-up effect due to the oversized resistivity between the second source 108a and the substrate junction 214.
When a current from the ESD reaches the drain 206 via the contact 212 of the drain 206, the current can pass through a channel 220 controlled by each projecting part 202 to reach the first source 208 or the second source 208a. It can be directed to a ground (not shown) via the contact 212 or directed to a substrate 210 via the substrate junction 214 in order to achieve a grounding effect.
As the butting contact 218 is simultaneously in contact with the second source 208a and the substrate junction 214, the resistivity between the second source 108a and the substrate 214 is rather small. Although the latch-up effect will not happen with a smaller resistivity, most of the current moves in the direction with less resistance, for example, to the substrate junction 214, after the current from the ESD reaches the drain 206 via the contact 212. In this case, the current that flows through the region adjacent to the butting contact 218 may become too large and a punch through can easily happen. The ESD protection device, which is located adjacent to the butting contact, is thus more prone to damage.